1. Field of the Invention
The Present invention relates to the field of integrated circuits. In particular, it relates to power management in programmable logic integrated circuit devices.
2. The Prior Art
Programmable Logic Devices (PLDs) are known in the art. A PLD comprises any number of initially uncommitted logic modules arranged in an array along with an appropriate amount of initially uncommitted routing resources. Logic modules are circuits which can be configured to perform a variety of logic functions like, for example, AND-gates, OR-gates, NAND-gates, NOR-gates, XOR-gates, XNOR-gates, inverters, multiplexers, adders, latches, and flip/flops. Routing resources can include a mix of components such as, for example, wires, switches, multiplexers, and buffers. Logic modules, routing resources, and other features like, for example, I/O buffers and memory blocks, are the programmable elements of the PLD.
The programmable elements have associated control elements (sometimes known as programming bits or configuration bits) which determine their functionality. The control elements may be thought of as binary bits having values such as on/off, conductive/non-conductive, true/false, or logic-1/logic-0 depending on the context. The control elements vary according to the technology employed and their mode of data storage may be either volatile or non-volatile. Volatile control elements like, for example, SRAM bits, lose their programming data when the PLD power supply is disconnected, disabled or turned off. Non-volatile control elements like, for example, antifuses and floating gate transistors, do not lose their programming data when the PLD power supply is removed. Some control elements, such as antifuses, can be programmed only one time and cannot be erased. Other control elements, such as SRAM bits and floating gate transistors, can have their programming data erased and may be reprogrammed many times. The detailed circuit implementation of the logic modules and routing resources can vary greatly and must be appropriate for the type of control element used.
An end user's PLD design is typically implemented by use of a computer program product (also known as software or, more specifically, design software) produced by the PLD manufacturer and distributed by means of a computer-readable medium like, for example, providing a CD-ROM to the end user or making the design software downloadable over the internet. Typically the manufacturer supplies a library of design elements as part of the computer program product. The library design elements provide a layer of insulation between the end user and the circuit details of the PLD features available to the end user like, for example, logic modules, memory blocks and programmable delay lines. This makes the design software easier to use for the end user and simplifies the manufacturer's task of processing the end user's complete design by the various tools in the design software.
Typically a user creates a logic design inside the manufacturer-supplied design software by entering schematics or describing it in a hardware description language like, for example, VHDL or Verilog. The design software then takes the completed design and converts it into the appropriate mix of configured logic modules and other programmable elements, maps them into physical locations inside the PLD, configures the interconnect to route the signals from one logic module to another, and generates the data structure necessary to assign values to the various control elements inside the PLD.
As semiconductor processing technology has advanced in recent years, transistor dimensions have continued to decrease. As a consequence, operating voltages for these small geometry transistors have also typically dropped—though this trend has slowed in the last few process nodes (130 nm, 90 nm and 65 nm) since the gate oxide thickness of the devices has not been scaled with the lateral transistor geometries in order to maintain operating voltages in the 1.0 volt to 1.2 volt range. The result has been transistors with very thin gate oxide layers, very short channel lengths, and low threshold voltages which produce substantially more leakage current than in previous generations. This has resulted in the static current of a CMOS integrated circuit typically becoming a substantial portion (and occasionally the majority) of the entire power budget. Dynamic power is also on the rise due to the ever increasing numbers of transistors that can be fit into an integrated circuit unmitigated by the traditional decreases in operating voltage.
As integrated circuit power consumption has been increasing, consumer demand for portable, battery-powered devices has also been on the rise. Power reduction is critical in such applications because battery life is a key component of both product usefulness and consumer acceptance. Even in non-portable systems, power reduction is an important issue in new electronic products by both semiconductor and systems manufacturers due to a variety of environmental concerns.
One response by the semiconductor industry is a design approach called Multi-Threshold CMOS (or MTCMOS). This is a loosely defined collection of design techniques which typically involves placing power or ground switching transistors in series with either the power or ground connection (or sometimes both) of various logic blocks to save leakage power when the blocks are not being used. Typically in MTCMOS the logic blocks are constructed with high-leakage/high-performance low threshold voltage (LVT) transistors and the power switches are constructed with low-leakage/low-performance high threshold voltage (HVT) transistors (hence the “multi-threshold” in MTCMOS), though often various parts of the circuit (in particular the logic blocks) are constructed with an optimized mix of LVT and HVT transistors. Sometimes a middle threshold voltage (MVT) transistor is also available giving the designer a choice of three different threshold voltages to use in trading off power and performance. A good summary of MTCMOS power switching techniques known in the art can be found in the WIPO published international patent application WO 2007/008579, which claims priority to U.S. provisional application 60/697,672.
PLD manufacturers have also been attempting to lower the power consumption of their parts and there have been a number of different families of PLDs and Field Programmable Gate Arrays (or FPGA—a type of PLD) which have one or more modes with reduced power consumption combined with reduced functionality (sometimes called a “standby” mode or a “low-power” mode or a “power-down” mode or a “sleep” mode) that the part can be placed in to reduce power when normal operation is not required. Reducing the power in the low-power mode or modes is critical in portable applications because typically the PLD will have long periods of inactivity and the static current during these times can be the majority of the total cost of the PLD to the battery life of the system.
FIG. 1 shows a system using a PLD of the prior art. In FIG. 1, PLD 100 has a PLD core 102 and a power control block 104. User logic 106 is programmed into the PLD core 102. There is a source of external system control logic 108 coupled to the power control block 104 in PLD 100 by interconnect 110. In order for the external system control logic 108 to place PLD 100 into sleep mode, a signal must be asserted on interconnect 110.
One drawback of this approach is there is no means of communication between power control block 104 and user logic 106. This means that there is no way for the PLD 100 to shut itself down in an orderly fashion relative to whatever is transpiring in user logic 106 at the time the sleep mode request is received in power control block 104. To achieve an orderly shutdown by stopping clocks and preserving the contents of sequential elements (like, for example, latches, registers, internal SRAM blocks, etc.) inside PLD core 102, then at least one optional interconnect 112 must be coupled between external system control logic 108 and user logic 106. This means that the designer of external system logic 108 must be familiar enough with the workings of user logic 106 to correctly generate the signals on optional interconnects 112 with respect to the signals on interconnect 110.
One commercial family using the general approach of FIG. 1 is the Spartan 3 family of FPGAs from Xilinx, Inc. of San Jose, Calif., which have both a “suspend” mode and a “hibernate” mode. In suspend mode, all of the SRAM configuration bits and the various sequential elements (latches, flip/flops, SRAM blocks, etc.) keep their logic states and some sources of quiescent power are turned off in response to a signal on a single pin. In hibernate mode, external power switches placed between the system power supplies and some or all (depending on the part) of the power supply pins of the FPGA effectively isolate them from the system power supplies (not shown in FIG. 1). Another commercial family using the FIG. 1 approach is the MachXO PLD family from Lattice Semiconductor Corporation of Hillsborough, Oreg. The MachXO family has a low-power mode where the power is reduced and the user logic is not functional in response to a single pin.
Xilinx experimented with the Spartan 3 PLD core attempting to reduce its power consumption and published the results in the paper A 90 nm Low-Power FPGA for Battery Powered Applications by Tuan et al presented at the FPGA '06 conference held in Monterey in February, 2006. According to the paper, Tuan et al produced a core that was compatible with the existing Spartan 3 software and existing process technology available to Xilinx. They made a number of hardware modifications, including reducing the voltage for the logic and routing portion of the PLD core from 1.2 Volts to 1.0 Volts, adopting the Virtex 4 FPGA family process for its middle oxide transistors to reduce gate leakage in the configuration SRAM bits, putting ground switch transistors in series with the ground connection of each repeatable tile in the core (a Spartan 3 tile is four logic modules and four flip-flops and the surrounding routing resources and support logic), and adding a configuration and power controller capable of saving the state of the core and manipulating the power switches by means of the configuration SRAM.
According to the paper, Tuan et al also modified the design software to exploit the hardware changes. A standby mode is available by storing the state of the flip-flops in configuration SRAM bits and then powering down all of the repeatable tiles by writing the appropriate value into the SRAM bits controlling the ground switch transistors. A partial standby mode is attained by selectively leaving certain tiles (and the logic and routing they contain) powered up so that a portion of the logic can be active during standby mode.
While Xilinx attained a considerable degree of power reduction success in the experiment, there is still room for improvement. According to the paper, Tuan et al considered improvements to the homogenous Spartan 3 derivative PLD core architecture and improved both the active and standby power significantly. Unfortunately, their implementation of partial standby mode leaves at least a portion of the regular PLD core active—albeit a reduced power PLD core. The larger the amount of logic required to be active during partial standby mode, the more costly it will be in terms of battery life since the PLD core isn't optimized for minimum leakage when active.
Also according to the paper, Tuan et al used a fairly fine grain in their minimum power switching unit—a Spartan 3 tile with four logic modules. Having many small regions like a Spartan 3 tile that can be powered up or down substantially increases the area required by the ground switch transistors. This contributes directly to power by increasing the area of the PLD core making wires longer and having more capacitance to drive in the active mode. Further, the amount of leakage in standby mode is directly proportional to the width of the ground switch transistors, so it is important to size them correctly. In a practical design, the ground switch transistors must be sized for the peak current they need to supply. Typically this is determined by running simulations on benchmark designs and observing maximum switching frequencies. With a coarse grain power-down block having a statistically significant number of logic modules, the size of the ground switch transistors can be tuned very closely to the real switching needs. In a fine grained block like the Spartan 3 tile with four logic modules, prudence would dictate allowing for at least two of the logic modules to switch simultaneously, which translates to sizing the ground switch transistors for an effective maximum switch rate of 50% which is too high to attain the minimum leakage current in standby mode.
FIG. 2 shows another system using a PLD of the prior art. In FIG. 2, PLD 200 has a PLD core 202 and a power control block 204. User logic 206 is programmed into the PLD core 202. There is a source of external system control logic 208 coupled to the power control block 204 in PLD 200 by interconnect 210. In PLD 200, interconnect 210 also couples to user logic 206 in PLD core 202, and one or more interconnects 211 couple between power control block 204 and user logic 206.
This approach overcomes a drawback to the PLD architecture of FIG. 1, since only a single interconnect line needs to be coupled between external system control logic 208 and PLD 200. When the external system control logic 208 signals PLD 200 to go into sleep mode by signaling on interconnect 210, user logic 206 can monitor the signal, place itself in a state appropriate for an orderly shutdown, communicate back and forth with the power control block 204 on interconnects 211, and then turn control over to power control block 204 to place PLD 200 in sleep mode. To wake up, power control block 204 receives a signal on interconnect 210 and wakes up the PLD 200 and initiates an orderly start in conjunction with the user logic 206. Thus external system control logic 208 can be designed without any detailed knowledge of user logic 206.
One commercial family using the general approach of FIG. 2 is the Igloo family of FPGAs from Actel Corporation of Mountain View, Calif., which has a “flash-freeze” mode. In flash-freeze mode, all of the various sequential elements (latches, flip/flops, SRAM blocks, etc.) keep their logic states since the PLD core remains powered up, however all clocks are shut off and certain circuits are placed in a low-power state.
One drawback to the approach of FIG. 2 is that there is still the need for external system control logic 208. This is undesirable since one of the purposes of using a PLD or FPGA in many applications is to consolidate all of the miscellaneous system logic into a single chip which is not possible in any commercial PLD with a low-power or sleep mode of the prior art.